Mon May 08 15:03:26 2000 vim:ft=vhdl: ---------------------------------------------- http://rassp.scra.org/vhdl/guidelines.html http://www.doulos.co.uk/hegv/index.htm ... VDHL tut. (not here). ---------------------------------------------- http://www.doulos.co.uk/reference/vhdlcard.htm -- Syntax Reference -- single line comment \n package Pack is type Enum is (Unknown, '0', '1'); type Int is range 0 to 255; type float is range 0.0 to 1.0; type Byte is array (7 downto 0) of Bit; type Mem is array (Integer range <>) of Int; type Intx is record Value : Integer; Defined : Boolean; end record; constant C1 : Int := 255; constant CV2 : Mem (0 to 511) := (1, 2, 3, others => 4); procedure P (Const : T; Var: out T; signal Sig : inout T); function "+" (L, R: T) return T; end Pack; package body Pack is procedure P (Const : T; Var: out T; signal Sig : inout T); -- declarations begin -- sequence of statements end P; function "+" (L, R: T) return T is -- declarations begin -- sequence of statements return Expr; end "+"; end Pack library Lib; use Lib.Pack.all; entity Ent is generic (G : Time := 0 ns); port ( P1 in T; P2 : out T := '0'; P3, P4 : inout T); end Ent; -- Behavioural description architecture A 1 of Ent is signal Sig1, Sig2: Typ := Init; begin Proc: process (Ck, D) -- declarations begin -- sequence of statements end process Proc; process variable Var : Typ := Init; begin wait until Rising_edge (Ck); wait for 10 ns; wait; Sig <= Expr after Delay; Sig <= Expr1 after D1, Expr2 after D2, Expr3 after D3; Var := Expr; case C is when C1 => -- sequence of statements when C2 | C3 | C4 to C8 => -- sequence of statements when other => null; end case; if Reset then -- sequence of statements elsif Ck'Event and Ck = '1' then -- sequence of statements else -- sequence of statements end if; for i in 1 to N loop -- sequence of statements exit -- sequence of statements end loop; while C loop -- sequence of statements end loop; assert D'stable (10 ns) report "Setup error" severity warning; report "End of simulation" end process; L1 : Sig1 <= A + B after 100 ns; L2 : Sig2 <= A * B after 1 us; end A1; architecture A2 of Ent is component Comp generic (G: Time := 0 ns); port (A, B: in T := '0'; F : out T); end component; signal S1, S2, S3: Typ := Init; begin L0 entity Lib.Ent2(Arch) port map (S1, S2, S3); L1: Comp port map (S1, S2, S3); L2: Comp generic map (G => 5 ns) port map (S1, S2, S3); end A2; configuration Cfg1 of Ent is for A1 end for; end Cfg1; library Lib; use Lib.all; configuration Cfg2 of Ent is for A2 for all: Comp use configuration Lib.Cfg3; end for; end for; end Cfg2; -- Expressions, Operators and Names () TypeName() ** abs not * / mode rem + - & sll srl sla sra rol ror = /= < <= > >= and nand or nor xor xnor 123 1_2_3 1e6 2#1110# 16#FF# "0101" O"77" X"FF" ABC def Ghi A123 A_B_C Name(Expr) Name(Expr1 to Expr2) T'Low T'High T'Image A'Range A'Reverse_Range S'Event S'Stable(T) S'Delayed(T) E'Path_Name -- Reserved Identifiers abs exit not signal access file null shared after for of sla alias function on sll all generate open sra and generic or srl architecture group others subtype array guarded out then assert if package to attribute impure port transport begin] in postponed type block inertial procedure unaffected body inout process units buffer is pure until bus label range use case library record variable component linkage register wait configuration literal reject when constant loop rem while disconnect map report with downto mod return xnor else nand rol xor elsif new ror end next select entity nor severity -- The STANDARD Package package Standard is -- (Library Std) type Boolean is (False, True); type Bit is ('0', '1'); type Character is (NUL, SOH, STX, ..., ' ', '!', '"', '#', '$', '%', '&', ''', '(', ')', '*', '+', ',', '-', '.', '/', '0', ..., '9', ':', ';', '<', '=', '>', '?', '@', 'A', ..., 'Z', '[', '\', ']', '^', '_', '`', 'a', ..., 'z', '{', '|', '}', '~', DEL); type Severity_level is (Note, Warning, Error, Failure); type Integer is range implementation_defined; type Real is range implementation_defined; type Time is range implementation_defined units fs; ps = 1000 fs; ns = 1000 ps; us = 1000 ns; ms = 1000 us; sec = 1000 ms; min = 60 sec; hr = 60 min; end units; function Now return Time; subtype Natural is Integer range 0 to Integer'high; subtype Positive is Integer range 1 to Integer'high; type String is array (Positive range ) of Character; type Bit_vector is array (Natural range ) of Bit; end Standard; -- The TEXTIO Package package textio is -- (library std) type line is access string; type text is file of string; type side is (right, left); subtype width is natural; file input : text is in "std_input"; file output : text is out "std_output"; -- in read and write below, type t is one of... bit, bit_vector, -- boolean, character, integer, real, string, time procedure readline(file f: text; l: out line); procedure read(l:inout line; value: out t); procedure read(l:inout line; value: out t; good : out boolean); procedure writeline(f : out text; l : inout line); procedure write(l : inout line; value : in t; justified: in side := right; field: in width := 0 digits: in natural := 0 unit: in time := ns); -- function endfile(f : in text) return boolean; end textio; -- The std_logic_1164 Package package Std_logic_1164 IS -- (Library IEEE) type Std_ulogic is ( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-'); type Std_ulogic_vector is array ( natural range ) of std_ulogic; function Resolved ( s : std_ulogic_vector ) return std_ulogic; subtype std_logic IS resolved std_ulogic; type std_logic_vector is array ( natural range ) OF std_logic; subtype X01 is resolved std_ulogic range 'X' TO '1'; -- also subtypes X01Z, UX01, and UX01Z function "and" ( l : std_ulogic; r : std_ulogic ) return UX01; -- also "nand" "or" "nor" "xor" "xnor" "not" -- also defined on std_ulogic_vector and std_logic_vector function To_* (S: *) return *; -- from bit bitvector StdULogic StdLogicVector std_ulogic_vector -- to bit bitvector StdULogic StdLogicVector std_ulogic_vector X01 X01Z UX01 function rising_edge (signal s : std_ulogic) return boolean; function falling_edge (signal s : std_ulogic) return boolean; end Std_logic_1164; ---------------------------------------------- -- VHDL 93 UPDATE http://www.doulos.co.uk/reference/update93.htm -- The most visible change - statement bracketing -- The syntax used to bracket entities, components, processes etc, is now -- consistent, as shown below... entity Name is ... end entity Name; architecture Name of EntityName is ... begin ... end architecture Name; configuration Name of EntityName is ... end configuration Name; package Name is ... end package Name; package body Name is ... end package body Name; component Name is ... end component Name; procedure Name is ... begin ... end procedure Name; function Name return Mark is ... begin ... end function Name; Label: process (...) is ... begin ... end process Label; Label: ... generate ... end generate Label; Label: if ... then ... end if Label; Label: case ... is ... end case Label; Label: ... loop ... end loop Label; type Name is record ... end record Name; -- The VHDL 93 syntax is upwardly compatible with the VHDL 87 syntax so -- the new keywords, names and lables may be omitted. -- -- The most significant change - direct instantiation Design entities can -- now be instantiated directly, rather than indirectly via components. -- Thus, a design hierarchy can be described without needing to write any -- component declarations or configurations! The new syntax for -- instantiation is... Label: component CompName port map (...); Label: entity EntName port map (...); Label: configuration ConfigName port map (...); -- For example, to instantiate a entity BLOCK_1 on the working library... G1: entity work.block_1 (rtl) port map (A, B, F); -- Also the rules for configuration have been clarified such that an -- empty configuration declaration is unnecessary to force default -- configuration. -- The incompatible change - file declarations The new syntax for file -- declarations is incompatible with VHDL 87. This means that any code -- using TEXTIO must be re-written... file F : TEXT is "NAME"; -- VHDL 87 or 93 file F : TEXT is in "NAME"; -- VHDL 87 only file F : TEXT is out "NAME"; -- VHDL 87 only file F : TEXT open READ_MODE is "NAME"; -- VHDL 93 file F : TEXT open WRITE_MODE is "NAME"; -- VHDL 93 file F : TEXT open APPEND_MODE is "NAME"; -- VHDL 93 file F : TEXT; -- VHDL 93 -- Explicit file open and file close procedures are provided too, so that -- you can be explicit about when a file is opened or closed... file_open (status, -- out open_ok | status_error | -- name_error | mode_error F, -- the file External_name, -- in String Open Kind); -- in READ_MODE | WRITE_MODE | -- APPEND_MODE file_close(F); -- The most controversial change - shared variables. Variables may be -- shared between processes, and thus used for inter-process -- communication. Variables declared outside processes must include the -- keyword shared, for example... shared variable V : Integer; -- However, any non-trivial use of shared variables is illegal in VHDL 93 -- ! A supplementary standard 1076a defines how shared variables my be -- used. -- Other useful changes - new attributes -- There are several new pre-defined attributes, including... T'IMAGE(X) -- Wher T is a scalar type. Returns the value of X represented as a -- string. Really useful for writing out values of user defined types to -- a text file. T'VALUE(X) -- The inverse of T'IMAGE, and thus useful when reading in text files. T'ASCENDING -- TRUE if and only if the range of the type T is ascending. Useful for -- writing utility subprograms that operate on vectors. E'PATH_NAME -- Where E is anything. Full hierarchical p[ath name of the item (e.g., -- "ent:comp:comp:sig"). Useful when writing out messages. -- There is a new attribute defined in package STANDARD... attribute FOREIGN : String; -- This attribute may be attached to an architecture or a subprogram to -- indicate that it is foreign (i.e., defined outside VHDL) -- The report statement -- In VHDL 87, one frequently writes something like this... assert FALSE report "Simulation finished with no errors."; -- A new statement is provided in VHDL 93 to make the assert FALSE bodge -- unnecessary... report "Simulation finished with no errors."; -- New operators -- There are seven new built-in operators... xnor -- defined on Boolean, Bit, Bit_vector -- Std_logic, Std_logic_vector sla sll sra srl -- Shift left or right, logical or arithmetic rol ror -- Rotate left or right, left operand is a -- vector, right operand is an Integer. -- Bit string literals -- Values of types such as std_logic_vector can now be written in -- hexadecimal or octal, as well as binary strings of 0's and 1's. For -- example... "100_111" = O"47" "1010_1111" = X"AF" -- Conditional signal assignments -- The else branch may be omitted from a conditional signal assignment, -- and both conditional and selected signal assignment statements can use -- the keyword unaffected to uindicate that the output is unchanged. Thus -- it is now possible to describe latches and flip-flops using short -- concurrent statements, for example... Flipflop: Q <= D when Rising_edge(clock); Latch: Q <= D when Enb = '1'; Counter: Q <= unaffected when Hold = '1' else Q + '1'; -- Specialised changes -- VHDL 93 contains many highly specialised or obscure changes, some of -- which are listed below... For inertial delay mode, the pulse rejection -- region can be defined independently of the delay for example... F <= reject 5 ps inertial A nand B after 10 ps; -- Processes can be postponed such that they only execute immediately -- before simulation time is advnaced, i.e., after all signals have -- settled to a steady value within each time step. This is usefu when -- checking for illegal combinations of signal values, because glitches -- that occur at intermediate delta times are ignored. -- Functions can be declared to be impure or pure. Impure functions may -- have side effectes (changing the values of extwernal variables), -- whereas pure functions do nothing but return a vlue. For example... impure function RANDOM return REAL; -- A generate statement may contain a declaration as well as statements -- This waas added so that configuration specifications may be used for -- example... for i in 0 to 7 generate for all: Comp use entity Lib.Comp; begin L: Comp port map (...); end generate G; -- Aliasing is generalised such that anything can be aliased. For example... alias "nand" is IEEE.Std_logic_1164."nand" (Std_logic, Std_logic) return Std_logic; -- Groups of VHDL constructs can be defined to pass information through -- to downstream tools, for example... group PinToPin is (signal, signal); group G1 : PinToPin (Clock, Q); -- All statements can now be labelled, including sequential statements. -- Extended identifiers allow any printable character to be included in a -- name. Extended identifiers start with a backslash and end with a -- backslash, for example... \A.$%^&*()\ -- Hey, guys! This is NOT Awk! ----------------------------------------------