Topic 04: Mano's Simple Computer

CSI404 Process vocabulary (process here means management rules for human activity.  Process is sometimes called "workflow" in business offices), the subject of first 1/4 of semester and covered in the exam, reviewed.

specifications
implementations

These are OBJECTS (nouns)

to design:  input a specification, output an implementation
to analyze: input an implementation, output a specification
to verify: input a specification and implementation (together), output OK or  bug reports

These are ACTIVITIES (verbs)

Software Engineering Institue (SEI) Capability Maturity Model  (CMM) for

Software Engineering Processes and how to evaluate (i.e., rate them for quality) and improve them.

Computer Architecture Vocabulary, division of this subject used by Hennessy and Patterson, for example.  (a little different since the term "design" is reused.)

Instruction Set Architecture: What programmers (of compilers, assemblers and operating systems, but not applications today) need to know.  That is the particular computer's machine language".  "Assembly Language" means almost the same thing.   (Ask yourself:  What is the difference between machine and assembly language?)

Machine instructions, registers, hardware supported datatypes (2-s complement integers, unsigned integers, floating point numbers), memory model, addressing modes.

Computer Organization:  Structure of high level parts.

Registers, Arithmetic Logic Unit (ALU), caches, memory, control units, Central Processing Unit (CPU),...

Computer Design: Low level structure of each part.

Gates, flip-flops, logic arrays, ...

Function and Structure compared in building (house) architecture.  Instruction set architecture is the function part of computer architecture.

Five classic components of a computer from Patterson and Hennessy: Control, Datapath, Memory (with different types with their different speeds), input and output.  The control and datapath comprise the processor, or CPU.

Register: Group of flipflops.  Block diagrams of registers (Mano fig. 4-1) Register Transfer Language statement R2 <- R1.
Meaning of "R2 <- (something)" in terms of gates and flip-flops (Mano fig. 2-7).  Analysis of that figure.
 

Functional Specifictation

Value of "Load" input	Data in register at next clock step R(t+1)
1	I (Data on input wires I)
0	R(t) (Data in register during previous clock step)

The control condition on the left side RTL statements and preceeded by ":" is sometimes called a guard.
When there is RTL statement with a true guard and destination R, then register R keeps its previous value.

Instruction Set Architecture of Mano's basic computer: Data is MORE IMPORTANT than processing, so the state of the Mano computer is described first.

Memory and Registers:  PC[11..0], E[1], AC[15..0], Memory (4096 words, each 16 bits, word addressed.  Ask yourself: How many bytes?  Compare to the 4GB virtual memory of suitably equipped PC's.
(Input/Output registers:  OUTR, INPR, FGO, FGI)

The Accumulator is like a single programmer visible general purpose register.  The MIPS computers and other RISC computers have 31 general purpose registers, plus one constant 0 register.

Data Types:  Integer 16 bit 2-s complement arithmetic operations, bitwise logic operations.  8 bit characters are supported only for I/O.

Instruction Format: See Figure 5-5 and Tables 5-? or 6-1.  Explanation of the I (for indirect addressing)bit and division of the first 4 bits into the I bit and a 3 bit opcode.

Detailed walkthrough of the Mano computer executing the first 2 instructions from the homework assignment, Mano's tables ?-? and ?-?.  Advice for the homework:  Read tables 5-? and 6-1 and for each entry, study enough of the text to understand it.

Organization of Mano's computer began.
Demonstration of ADD instruction with direct and indirect addressing.
Addresses are like house numbers; they numbers but they are different from memory contents.
Addresses are values of C/C++ pointer variables
Walkthrough of what the computer does on a numeric example given by the students.
Activity of one instruction cycle visible to programmer when it handles an ADD instruction:
1. The sum replaces the current contents of the AC register
2. The carry out from the summing replaces the current contents of the single bit E register.
3. The computer is set up to next execute the instruction right after the ADD instruction in memory.  That is, the program counter (PC) is incremented by 1.
Indirect addressing discussed.
Which instructions modify or reset E register is not clearly stated in Mano's functional specification unfortunately.
(The implementation does resolve these details, which is not ideal.)
Explanation of Figure 5-4 from Mano.
Flowchart of the common steps of the instruction cycle (the instruction cycle is different from the clock cycle)

The SC<-0 and first 2 steps of the instruction cycle.  When register state changes occur based on clock waveform.
Sequence cou nter (SC) register and the 4X16 decoder which generates the timing signals T0, T1, ...

Mano Instruction Set Architecture functional specification: quick review.
Registers and common data bus used in its implementation (Mano's fig. 5-4).
Register Transfer Language statements:

See and learn to use Mano's table 5-6.
Combinational signal definition statetment

Uses an = sign.
Examples: D7I'T3 = r;   IR(i)=Bi foi i=0,...,11
Means an abbeviation and/or some combinational circuit to generate the signal named by the defined symbol.

Register Transfer Statement

Example:  rB7:  AC(14...0)<-shr AC, AC(15)<-E, E<-AC(0)
Has control function or "guard" plus general microoperations.
The comma separated list of general microoperations are all performed simultaneously in those clock periods in which the guard is true.
Illustration of the action of the above example on an example.
Specific microoperation (register transfer): numeric data generated and transferred to a register.
General microperations in the hardare description require hardware be built (in silicon) capable to do it:  Each is 1 register transfer, done in  1 clock step.
Specific microoperation: you show the  number calculculated and trasferred!

The sequence counter register and timing signal decoder:  Waveforms of T0, T1, ... (fig. 5-7)
The Mano machine organization flowcharts common steps:  Graphic description related to textual RTL statements.
Timing signals, data transfers and use of the common data bus during the T0: AR<-PC operation.

Implementation of the common data bus with MUXs, review of MUXs and their applications.
 

Mano's computer organization uses a hardwired control unit.  Hardwired control units were a popular organization style of 1960-early 70's computers.  The mid-70s to 80s computers used microprogrammed control units in computers with CISC style instruction set architectures.  CISC means Complex Instruction Set Computer.  Optional reading for now: Mano chapter 7 on microprogrammed control units.  Late 80s to present computers which used the RISC (reduced instruction set computer) instruction set architecture style have gone back to the hardwired control unit organization.  The advantage of hardwired control over microprogrammed control is speed for the same amount of functionality.  The advantage of microprogrammed control is cost and design/debugging convenience for more complex functionality.
The 3 steps of the fetch phase shown on the flowchart, RTL table, with block diagram  of the relevant  registers.
The 3 to 8 instruction code decoder.
Detailed explanation of when combinational circuits operate and when register outputs change in  terms of the clock waveform.
Walkthrough of the LDA instruction in all the figures, treating both indirect addressing and direct addressing forms.
Brief explanation of the ADD instruction implementation in terms of its small differences from the LDA instruction.

ALU construction.
Terms "store" and "mill" used by Babbage in programmable computer designs in 19th century.
Zero detect implemented with an OR gate.
How control signals to the ALU selects the particular operation.

Comparative Instruction Set Architecture (brief)

Operand Storage in the CPU (Register Organization, Stack Organization)
Instruction Formats, Addressing modes
Program Control(Application Level)

Distinction between (1) assembling and (2) running an assembly language program.
Person writes assembly language program->Assembler->object or excecutable file->machine language program in computer's memory->run of the program (when "Start" button is pressed).
Mano's sample program assembled and demonstrated.
Mano's instruction set architure's subroutine linkage support (BSA and BUN I instructions)
Subroutine linkage support in other Instruction set Architectures use memory stack (Pentium) or a register (MIPS) to hold return address.
What assemblers do (flowcharts of their two passes, examples of forward referencing symbols )

•  Slide image 1 progress of the Assembler through a sample assembly language program(.jpg)
•  Slide image 2 steps in creating and later running a program: STATIC versus DYNAMIC(.jpg)

Long explanation of the distinction between static and dynamic phenomena.
Space time tradeoff:  Todays software is better if the static code size is LARGER and the (dynamic) execution time is SMALLER.  For example, people would rather buy software on a CDROM that runs fast than similarly functioning software that fits on a floppy disk but runs slower.
Walkthrough of some execution and some work done by each assembler pass with Mano's example that demonstrates a subroutine to Circulate-Left-AC-and-E 4 times.
Dynamic explanation of the execution of 4 successive CIL instructions.
Discovery of a bug in Mano's comment: Set AC(13-16) to zero should be Set AC(3-0) to zero.
Symbols, what they symbolize, symbol table, dynamic behavior of assembler's LC variable.

REALLY DO Mano Basic Machine's I/O Architecture.
Interrupts:  their relation to BSA on Mano's basic computer.
Busses:  Alternative inplementation with tri-state drivers.