• Introduction to the sequence diagram formalism (from Unified Modeling Language, part of the standards advocated by the Object Management Group, who also sponsor Common Object Request Broker Architecture (CORBA).

Page from the UML 1.3 specification: example of a sequence diagram to show the activities of a caller, exchange and receiver in initiating a telephone conversation.  The actions of each object are plotted along vertical "railroad tracks".  Time advances (toward the future) downward.   Interactions or messages are expressed by labelled horizontal arrows.
•  Sequence Diagram Example from UML 1.3 (shown in class, plus adjoining explanations, .ps)

Registers used for I/O in  Mano's basic computer: Mano's figure 5-12 plus IEN and R (ignore IEN and R for next 2 lectures).

Need to signal printer to print the character from OUTR in addition to copying the new character there.

Sequence diagram for printing a character drawn on blackboard.

Time to print a character on an inkject printer (0.001 sec. = 10^-3 sec.) compared to clock cycle times of computers

(Late 60's: < 10^-6 sec, 2001: 10^-9 sec).  Mano computer could execute 500 instruction or so between printing two characters.

Mano assembly code seq (Table 6-19) to output one character.

RTL description for output instructions:  OUT and SKO; related to the registers.

• Interest and importance of input/output; there are roughly 10 times more computers in embedded applications than in PCs.  Embedded applications include engine state sensing and control in automobiles.
• Programming Mano Computers for input and output:  Table 6-19.  Description of activity during the run of the output program by a sequence diagram (on a slide).
• BUSY WAITING explained:  Mano's program makes the computer loop while waiting for the printer to print one character.
• Input explained too, in terms of Table 6-19.  Registers for input analogous to output.
• Mano's codes include echoing so the character input on the keyboard is displayed to the user.  Echoing is needed on typical UNIX full duplex terminal connections.  Echoing might be turned off for applications such as password security.
• Mano's code unfortuately does not synchronise the output operations for echoing.  Hence it can fail if the keyboard is faster than the printer.
• Current homework problem 4:  Write a blocking input subroutine to read n characters.  Ordinary input commands such as

cin >> stringvar;   (C++)
read( fd, pchar, N )   (Unix/Posix system call)
are blocking.  Blocking means the subroutine does not return until the input is complete.
• Default UNIX terminal input blocks until a newline is entered.  CSI402 teaches how to override this.
• Figures 11-1 and 11-10 from Mano:  Multiple interfaces and devices use a bus to connect to the CPU.  In modern computer systems, the data and control registers (analogous to INR, OUTR, FGI and FGO) reside in the interface, not in the CPU.
• Flowchart for inputting:  Mano's figure 11-11, shows inner loop that busy waits until data is ready, plus outer loop that runs until the whole operation is complete.  (The transaction details differ from Mano's Chapter 6 architecture.)
• Summary of Mano's Basic Computer's registers below:

Registers used for I/O in Mano's Basic Computer

Steps of an output transfer:

1. Initially, FGO=1
2. Computer checks FGO with SKO instruction, (see b on page 203)

        LDA   CHAR  /AC now contains the character to output
   COF, SKO         /Test FGO flag
        BUN   COF   /Loop if output device isn't ready.
        OUT         /Transmit character to output device.
3. Computer finds FGO=1
4. Computer executes OUT instruction, this sets FGO<-0
5. Output device starts to output the character

A VERY LONG TIME PASSES....(if the computer has another char, it will run the above loop)
6. Output device is ready to accept a new character; it sets FGO<-1 to indicate this.

Steps of an input transfer:

• Initially, FGI=0

A VERY LONG TIME PASSES..(the computer is running in the loop below)
• User supplies input, say a person presses a key.
• Device detects that FGI=0 and therefore "shifts" the 8 bit character into INPR.
• Device sets FGI<-1
• Computer checks FGI with the SKI instruction and finds it is 1. See page 203.

      CIF,   SKI       /Test FGI flag
         BUN  CIF  /Loop if FGI=0
         INP       /Now, input char is in the AC
         STA  CHAR /Copy input char into memory
         ...
  CHAR,  ---
and computer finds FGI=1
• Computer executes INP instruction, which copies char to AC and unsets FGI<-0

• Explantions of 3 ABIs (Application Binary Interfaces) for calling subroutines
1. MIPS: Return address in $ra, Argument(s) in $a0, $a1, ..., Return value is $v0, $v1

Callee saves registers $s0, $s1, ... .  Caller saves registers $t0, $t1, ... if necessary.
2. i386 (Pentium) Register $ESP points to an in memory stack.  Arguments and return address are pushed in this stack. Return value is passed on top of the stack.
3. Mano Basic (obsolete)
1. BSA TARGET  instruction stores return address in m[TARGET].  Subroutine might return via BUN TARGET I after adjusting the value m[TARGET] if necessary to "skip over" arguments
2. Sometimes argument and return value is passed through ACC.
3. Sometimes arguments are put in memory immediately after the BSA TARGET instruction.
4. Brief mention of stack partly in CPU hardware used by SPARC machines.  ("Register Windows" are described in Mano's book.)
• Discussion of how and why the ORG pseudo instruction controls the assembler, and its results are NOT STORED ANYWHERE.
• Complete subroutine and tester for blocking output, written in Mano Basic Assembly Language. It really works with the MANOASM and MANO2 assembler and simulator software!(text file)
•  The object file (writer.obj) output by the MANOASM assembler(text file)

Example of a race explained:  One process runs

LOOP, INP
      STA  PCH  I
      ISZ  PCH
      BUN  LOOP
      BUN  LOOP
PCH,  HEX  100
The other process has a person (or monkey) pressing keys, which make new data go into the INP register.
(Review of how this is assembled)
Run of these processes explained with a 2 rail sequence diagram:  It is indeterminate how many copies of each input character are stored in memory.
(direct and indirect addressing compared)

Some vocabulary:

• blocking (I/O operation); operation expressed by a function call that DOES NOT RETURN until the data transfer is complete.  (The I/O facilities taught in beginning programming courses are all blocking.)
• To Busy Wait: to repeatedly test a variable to determine when an operation can proceed.
• (true) Parallelism: 2 or more processes doing computations or data transfer AT THE SAME TIME.  (A job with several tasks will be finished faster if it can be parallelize.  Example: 100 people with shovels compared to 1)
• Processes:  the computations that might run in parallel.  A process is one "flow of control and data"
• Race: situation where the outcome DEPENDS on the relative timing of the operations done by several processes.
• Concurrency: 2 or more processes proceed "as if" they were parallel.  Concurrency without parallelism can be implemented by interleaving (also called time sharing) the processing on one processor.

Tri-state buffer devices explained:  When the control input C=0, the output is disconnected (high impedance).  Whe C=1, the output is connected to ground when data input D=0, and to the (high voltage) power source when D=1.

Role of tri-state buffers in computer busses.  Slots for plugging in peripheral cards mentioned.

to be supplied..

Lecture 28 (4/4)

Exam "interrupted"

• 3 modes of I/O transfer (Mano sec. 11-4)
• Programmed I/O (we did that)
• Mano's figure 11-11
• corrected: Read data register in first box should be Read status register.
• Busy wait loop:  loop when Flag=0
• corrected Read status register should be read data register
• Flowchart boxes correlated with Mano Basic assembly code.
• I/O register status flag likened to the signal flag on a rural mailbox.
• Interrrupt controlled I/O (covered below)
• Direct Memory Access I/O (to be covered later)
• Interrupts in Mano's Basic Computer
• ION and IOFF instructions to control the IEN register.
• Condition to set the R register
• Illustrated with UML sequence diagram
• The interrrupt cycle, analyzed on waveform diagram.
• Interrupt and function call (BSA) similarity in Mano's Basic Computer
• Two actions of interrupts:
• Kind of control transfer.
• CPU mode changes when an interrupt occurs: User mode becomes priviliged mode.
• Full-fledged computers have user mode instructions a subset of all their instructions. Priviliged instuctions encountered when the CPU is in user mode are NOT executed and cause an error action to occur.  (To be seen: that error action is to take an interrupt!)
• Glimpse at the timing diagrams for memory-CPU data transfer on the Pentium system bus (from the AMD processor manual)
•  Timing Diagram for Memory Read and Write(.ps)
•  AMD Processor Manual(.pdf)

Exam 2.

• Mano Basic Computer's subroutine call and return architecure (BSA to call, BUN  I to return) compared to its interrupt architecture.
Similarities: Return address is saved so the calling program's execution can be resumed.
Explained with Figures 5-10 and 5-14.
Current homework to write a non-blocking subroutine for doing input explained.
An interrupt service routine (called I/O program on figure  5-14) is the code written by system programmer that the computer will run when an interrupt occurs.  It is part of the I/O device's device driver.
• Skeleton interrupt service routine in Mano's Table 6-23.
Don't do output (since the support for parallel input and output in Mano's Basic Computer is not realistic).
Saving and restoring the contents of the AC and E bit.
• In the Mano Basic Computer, the return address from an interrupt is always saved in memory at address 0.  The interrupt service routine is always executed beginning at address 1.
• Other computers:
• i386 (IBM PC): The return address is pushed on an in-memory stack.  The interrupt service routine address (or a call gate) is fetched from a vector of them in memory, pointed to by a register.  The IRET instuction performs the return from an interrupt by popping the "Flags" word and the return address from the stack.
• MIPS (typical RISC): The return address is saved in a special system register (called Interrupt Return Address Register).  The interrupt service routine address is an address fixed by the hardware.  There is an IRET instruction.
• Glimpse at a the serial port device, which is a device in IBM PCs that is most like the Mano Basic keyboard and printer.
• It is the UART:  Universal Asynchronous Receiver and Transmitter device.  It operates the serial ports, through buffer amplifiers.
• Tables from The Indispensable Hardware Book (second edition), by Hans-Peter Messmer
• 11 Registers in this device (as opposed to 2 data registers and 2 control bits)
• Receiver  Buffer Register: like IN register.
• Transmit Hold Register: like OUT register
• Registers for controlling and identifying interrupts:
• Interrupt enable register: among its bits are one to cause an interrupt if the transmit holding register is empty, and one to cause an interrupt if received data is available.
• Interrupt identification register:  allows the interrupt service routine to tell what caused the interrupt.
• Tables of how the device driver writer can program the interrupt service routine to reset each condition that caused an interrupt.
Supplemental Material:
• References and explanations of the UART in the PC
• Signals (pins) of the UART, from Intel's databook pages 17-18 (.ps)
• UART Register and operation details, from Intel's databook, pages 97-114 (.ps)
• Intel's databook on the 82091AA ADVANCED INTEGRATED PERIPHERAL (AIP), document 290486-003, 29048603.pdf available from http://developer.intel.com

• Homework:  Read PH. Chapter 6, and Chapter 3 as necessary to become able to analyze the 5 stage MIPS pipeline behavior on given sequences of instructions.  Also, do problem 1, which will be to design a 1-bit 8-to-1 multiplexor that uses tri-state buffers instead of OR gates to generate its output; and explain how your design guarantees that one and only one buffer is enabled (put in a low-impedance output state) at a time.  Refer to material in Mano about tri-state drivers if necessary.
• Introduction to system busses.
• The electrical situation when two tri-state buffers driving the same bus wire are enabled simultaneously:  It is like short circuiting an electrical power outlet. (Some busses are designed to prevent hardware damage in case of inadvertent use conflicts, but data errors can still occur.)
• Modern computer systems are bus organized.  The CPU, memory controller and I/O controllers are connected to a common bus.
• The bus has an arbitration protocol which determines which device connected to the bus become the bus master.  The bus master determines the direction and destination of the data transfer.
• Modes of I/O transfer: (Mano sec. 11-4) These modes distinguish ways of solving the problem of synchronizing the parallel operation of the I/O device with the CPU.  I/O devices operate on a time scales that are typically much slower (by factors of thousands or more) than CPU operation.
1. Programmed.  Also called polling or busy-wait.

A loop to repeatedly test when the data transfer is complete is programmed.
2. Interrupt driven.

An interrupt service routine is pre-written and loaded with the operating system.  The interrupt service routine is activated by the hardware when the I/O device signals that the data transfer is complete or it otherwise needs servicing by the software.
3. Direct Memory Access.
1. Programmed register access to the I/O device instructs it to do an I/O operation to or from a given bus address.
2. The CPU runs in parallel with the operation of the I/O device.
3. When the I/O device has or needs data, it uses bus arbitration to become bus master.  The I/O device all by itself uses the bus to transfer data to or from the memory, via the memory controller connected to the bus.
4. When the data transfer is complete (or the I/O device needs software attention for other reasons, such as an error or failure), the I/O device uses the bus to signal an interrupt to the CPU.
• More on interrupts..
• An interrupt is a kind of jump or branch.  The first major difference between interrupts and programmed jumps, branches and subroutine calls is that for an interrupt, the target address is PRE-SET.  The target address is FIXED by either the hardware or configured by operating system software in a way that application software cannot change it (unless the system is "cracked", or the operating system is as primative as MSDOS which doen't use the CPUs protected mode.)  In the Mano Basic Computer, the interrupt return address is ALWAYS saved in memory location 0, and the interrupt target address is ALWAYS 001.
• Besides jumping, the hardware disables some or all subsequent interrupts when an interrupt is taken.  (The Mano Basic computer does this by the micro-operation IEN<-0.  The interrupt service routine would run the ION instruction to re-enable interrupts just before it returns.)
• In modern computers, an interrupt also makes the CPU change to privileged mode.  In privileged mode, all instructions are executed when they are encountered in the program run.  In user (non-privileged) mode, some of the instuctions become illegal.  When any kind of illegal instruction memory access is encountered, the CPU takes an exception.
• The action the CPU performs when an exception occurs is very similar to an interrupt!  So, when an instruction that is illegal because the CPU is in  user mode is encountered, the CPU will run the operating system's interrupt service routine instead of executing the illegal instruction.
• Some instructions are legal and normal to execute in user mode but have the purpose of causing exceptions.  Such instructions are called variously syscall, trap, break,  or int.  Their purpose is to enable application programs to make system calls.  A system call is for an application program to request operating system services.
• The C library system calls functions (taught in CSI402) such as read(.., .., ..) invoke ordinary function bodies that contain ordinary instructions (to prepare arguments in registers, etc) plus one syscall instruction.

Copyright (C) 2001 S.Chaiken, all rights reserved.
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