Topic 07: Memory Systems (caches)

• Technology, speed, cost trends: (from PHs 1st and 2nd editions)

 

Memory Technology	Typical access time (1993)	Typical $ per MByte in 1993
Static Random Access (SRAM)	8-35 nanosecond	$100-400
Dynmic Random Access (DRAM)	90-120 ns	$25-50
Magnetic Disk	10-20 Million nanoseconds	$1-2
	Typical access time (1997)	Typical $ per Mbyte in1997
SRAM	5-25 ns	$100-$250
DRAM	60-120 ns	$5-$10
Magnetic Disk	10-20 Million nanosec. (like 1993)	$.10-$.20 (10 times cheaper!)

• Quick glimpse at memory hierarchy HP figure 7.2
• Programmers use a uniform address space; but it is implemented by several different kinds of hardware with different speeds and costs/bit.

• Two achievments of post 1970's memory systems (different goals):
1. SPEED
• Locality of reference phenonemon:  part of the behavior of processes (single runs of software)
• Temporal and Spatial (definitions from PH ch. 7)
• Examples of their causes (loop code, loop indexes, array references in loops)
• Achieved thorough hierarchical memory systems
2. Virtual Memory: Practical (affordable) inplementations of HUGE and private addresses spaces for programming.
• Static RAM technology:  Same technology and clock the rest of the CPU uses
• See PH Appendix B.23 and B.24
• Feedback makes the data storage stable.
• Dynamic RAM uses capacitors, that is, static electricity to store information (charged for one binary value, uncharged for the other).
• Logical addresses (for the programmers) and physical locations (which hardware holds the data, also called addresses) compared.
• Tracing direct mapped cache behavior, misses and hits, from cache address trace (PH figure 7.6, example for homework)

• Levels of caches; the same logical address is used for each (separate) copy of the data with that logical address in each level cache where the data is allocated.
• Direct Mapped Cache Hardware and logical address decomposition
• Tag, Index and Offset on PH fig. 7.7
• Associative Memory
• How it is like "association" in  psychology.
• Much smaller physical size for a given address space
• More complicated and slow addressing hardware
• Cache with 4 words per block: PH Fig. 7.10
• Part of the homework answer.
• Virtual Memory:  Add magnetic disk hardware as another cache level below RAM. PH figure 7.20.
• PH figure 7.22 decomposition of virtual address (which is essentially the logical address) into page number and offset,
• What operating system does when the page containing a logical address is not allocated in RAM.
• Changing of the page table during a context switch implements privacy of virtual address spaces.

• Slides from IBM application notes and datasheets:
• Single DRAM read timing diagram.
• Typical 1996 DRAM performance specifications.
• EDO Mode read cycle
• Late 1999 Synchronous DRAM performance specifications
• Interface to older DRAM chips is asynchronous
• New Synchronous DRAM chips have more interface and control circuits built in, and their interface uses a clock signal.
• Simple synchronous DRAM single read cycle.
• Talk and example of error correcting code.

(C) Copyright 2001, S.Chaiken.  All rights reserved.;
$Id: Topic07.html,v 1.1 2001/05/03 16:14:27 sdc Exp sdc $