Messmer's Indispensable Hardware Book is a good place to begin to find hardware details relevant to systems programming of PCs. However it is as "secondary source" and has omissions and errors. Serious software developers will use primary documentation sources, such as the databooks from Intel or AMD. On the other hand, books like Messmer's, and "The Undocumented PC" will bring together facts about different hardware components. These facts are hard to gather separately. For example, Messmer's book describes on pages 873 and 887 how the INTR and OUT2# output signals of the UART chip are gated together to control the interrupt input to the PC bus, which is not documented in Intel's databook on a popular integrated peripheral chip that contains a UART. The material from Messmer's book appears on pages 881-883. This is part of section 29.2, pages 853-889 which covers asynchronous serial data transfer, the RS-232C interface, how it is used to connect computers with modems, printers and other computers; and finally how to program it through DOS, the PC BIOS, and registers of the 8250/16450/16550 UART chip. The following are excerpts from Intel's databook: 82091AA ADVANCED INTEGRATED PERIPHERAL (AIP), document 290486-003, 29048603.pdf available from http://developer.intel.com "The 82091AA Advanced Integrated Peripheral (AIP) is an integrated I/O solution containing a floppy disk controller, 2 serial ports, a multi-function parallel port, an IDE interface, and a game port on a single chip. The integration of these I/O devices results in a minimization of form factor, cost and power consumption." I have separated some of the sentences into different lines and added explanations in [square brackets]. The pages from which this material is taken are linked. There are 2 series: pages 17-18 which lists the signals (pins) on the 82091AA used by the two UARTs on that chip, and pages 97-114 which describes the operation of the serial ports in terms of their registers in detail. Registers of the UART relevant to the CSI404 introduction: Registers for OUTPUT: Transmit Holding Register (THR): (like Mano's Basic OUT register) TRANSMITTER HOLDING REGISTER STATUS (THRE): (like Mano's Basic Computer' s FGO register) This bit is the Transmitter Holding Register Empty (THRE) indicator. THRE indicates that the serial port module is ready to accept a new character for transmission. In addition, this bit causes the serial port module to issue an interrupt to the CPU when the Transmit Holding Register Empty Interrupt enable is set to a 1. THRE is set to 1 when a character is transferred from the Transmitter Holding Register into the Transmitter Shift Register. THRE is set to 0 when the CPU loads the Transmitter Holding Register. In the FIFO mode, this bit is set to a 1 when the transmit FIFO is empty, and is set to 0 when at least 1 byte is written to the transmit FIFO. This bit is the Transmitter Holding Register Empty (THRE) indicator. [Explain the name of the bit.] THRE indicates that the serial port module is ready to accept a new character for transmission. [Specfy the main part of the meaning for the bit.] In addition, this bit causes the serial port module to issue an interrupt to the CPU when the Transmit Holding Register Empty Interrupt enable is set to a 1. [Specify an additional meaning that an interrupt will be issues under certain conditions. The Transmit Holding Register Empty Interrupt Enable bit is specified elsewhere.] THRE is set to 1 when a character is transferred from the Transmitter Holding Register into the Transmitter Shift Register. [Specify a detail about how the serial port module is implemented.] THRE is set to 0 when the CPU loads the Transmitter Holding Register. [Specify the complementary condition about the detail above.] In the FIFO mode, this bit is set to a 1 when the transmit FIFO is empty, and is set to 0 when at least 1 byte is written to the transmit FIFO. [Modify the above two details when the serial port module is in a different mode that will provided higher performance.] Registers for the interrupt facility: INTERRUPT ENABLE REGISTER (IER) This register enables/disables interrupts for five types of serial port conditions. If a particular condition occurs whose interrupt is disabled in this register, the corresponding interrupt status bit in the IIR will not be set and an interrupt request (IRQ3 or IRQ4) will not be generated. It has 4 relevant bits: 3 MODEM INTERRUPT ENABLE (MIE): When MIE=1, the Modem Status Interrupt is enabled. When MIE=0, the Modem Status Interrupt is disabled. 2 RECEIVER INTERRUPT ENABLE (RIE): When RIE=1, the Receiver Line Status interrupt is enabled. When RIE=0, the receiver line status interrupt is disabled. 1 TRANSMITTER HOLDING REGISTER EMPTY INTERRUPT ENABLE (THEIE): When THREIE=1, the Transmitter Holding Register Empty Interrupt is enabled. When THREIE=0, the Transmitter Holding Register Empty Interrupt is disabled. 0 RECEIVER DATA AVAILABLE INTERRUPT ENABLE AND TIMEOUT INTERRUPT ENABLE IN FIFO MODE (RAVIE): When RAVIE=1, the Received Data Available Interrupt is Enabled. When RAVIE=0, the Received Data Available Interrupt is disabled. In addition, in the FIFO Mode, this bit enables the Timeout Interrupt when set to 1 and disables the Timeout Interrupt when set to 0. [These bit control which conditions detected by the serial port module will cause interrupts.] INTERRUPT IDENTIFICATION REGISTER (IIR): This register provides interrupt status and indicates whether the serial port receive/transmit FIFOs are en- abled (FIFO mode) or disabled (non-FIFO mode). In order to provide minimum software overhead during data character transfers, the serial port prioritizes interrupts into four levels and records these in the [this] Interrupt Identification Register. The four levels of interrupt conditions in order of priority are Receiver Line Status; Received Data Ready; Transmitter Holding Register Empty; and Modem Status. When the CPU accesses the IIR [this register], the serial port freezes all interrupts and indicates the highest priority pending interrupt to the CPU. While this CPU access is occurring, the serial port records new interrupts, but does not change its current indication until the current access is complete. Bits relevant to non-fifo operation: Bit 0: Interrupt Pending Status 1=No interrupt pending. 0=Interrupt pending Bits 1-2: Highest Priority Pending Interrupt [If bit 0 = 0, bits 1-2 code in binary the priority of the pending interrupt according to the priority order specified above. Notice that receiver interrupts have higher priority than transmitter interrupts because the computer has no direct control of the device sending input data to it, so the computer must respond to input first so that input data is not lost.] [See Table 22 on page 103 for all the interrupt causes, what priority each cause has, how that priority is coded by bits in the IIR, and what actions by the device driver software on the serial port will reset that interrupt cause.]