Tuesday May 2 Morning ===================== Ruediger Martin "Speculation techniques for improving load related instruction scheduling" Paper 1999 ISCA PH 4.3, 4.2/4.6, 5.3-5.5 -------------------------------------------------- Thursday May 4 Morning ====================== Li Qi An analysis of correlation and predictability what makes two level branch predictors work Evers, Patel, Chappell and Patt Proc 25 ISCA p.52-61 Li Qi's conclusions slide 8:45-9:10 AM ------------------------------------------- Chih-Yuan Cheng Architecture of the Pentium Processor Alpert and Avnon Readings in Computer Architecture p.649-659 PH. Ch. 2, 3 ------------------------------------------- Thursday May 4 11:15-12:35 Room SS-131 ================================= Haleh Najafzadeh Ph.D. Research Report: Source Code Instrumentation and its Perturbation Analysis in Pentium II (guest lecture in CSI500 course) Thursday May 4 2:30-3:30 Room BA-210 ================================= Tzu-Feng Huang Paper Title: A Study of Branch Prediction Stratategies Author: James E. Smith Publication: Readings in Computer Architecture Date: September 9, 1999 Pages: 214-227 Section Referenced: HP's text book, section 4.3 Reducing Branch Penalties with Dynamic Hardware Prediction P. 262-278 Slides ------------------------------------------- Shiqing Li Cashe-Conscious Data Placement Calder, Krintz, John and Austin ASPLOS 8, 1998 p.139-149 Ch 5.1 ------------------------------------------- Huimin Hu Software Pipelining and loop support of IA-64 Intel IA-64 book, Jan 2000 Vol. 1 chapter 11 http://developer.intel.com/design/ia-64/downloads/245317.htm My topic is the Intel IA-64 pipeline. PH. 4.5 ------------------------------------------- Li Ling Detecting Pipeline Structural Hazard Quickly Todd Proebsting and Christopher Fraser 1994 POPL PH 3.3, 3.9, matrix computation -------------------------------------------------- Tuesday May 9 Morning 8:00 to 9:45 AM ====================== Yiqiang Jin S. Tahar and R. Kumar Formal Verification of Pipeline Conflicts in RISC Processors 1994 ACM PH. pages 146-177 ------------------------------------------- Zhencai Wang Proceedings of the 8th international conference on Architectural support for programming languages and operating systems October 2 - 7, 1998 A Look at Several Memory Management Units, TLB-Refill Mechanisms, and Page Table Organization. Bruce L. Jacob and Tevor N. Mudge Paper Summary Slide ------------------------------------------- (Optional extra session Tues May 9 12:30-1:30 LI98 CS conf room) ================================================================= Feng Wang Storageless Value Prediction Using Prior Register Values Tullsen and Seng 26th ISCA 1999 ------------------------------------------- Lei Wang The Block based Trace Cache Black, Rychlik and Shen 1999 IEEE, p.196-207 Slides ------------------------------------------- Tuesday May 9 2:30-4:30 PM Room BA-213 ================================================ S.Krishnamoorthy IA-64 (Itanium) Superscalar architecture's (EPIC - Explicit Parallel Instruction Computing). I will be covering the Chapter 4, page 211-240 of Patterson & Hennsey. Since IA-64 has lot of topics for discussion, I will be convering the IA-64 Explicit parallelism in detail. Intel IA-64 documentation. C. Dulong, The IA-64 Architecture at Work, IEEE Computer July 1998, p.24-32. ---------------------------------------------------- Zailong Bian Stack, Evers and Patt Variable Length Path Branch Prediction 8 th ASPLOS 1998 p170-179 PH p. 262-271 --------------------------------------------------- Yuyan Liao Improving the Accuracy of Dynamic Branch Prediction Using Branch Correlation author: Shien-Tai Pan, Kimming So, Joseph T. Rahmeh publication: ASPLOS-V, Proceedings of the fifth international conference on Architectural support for programming languages and operating systems reference: HP chap. 4.3 --------------------------------------------------- Rong Zhang Smith and Pleszkun Implementing Precise Interrupts in pipelined processors. Readings in Computer Architecture, p.202-213 HP 3.6 p.178 --------------------------------------------------- Bruce Munro Improving Direct-Mapped Cache Performance by the addition of a Small Fully-Associative Cache and Prefetch Buffers N. Jouppi Readings in Computer Architecture ---------------------------------------------------